90 nm Current Mirror Based Transimpedance Amplifiers for Fiber Optic Applications *

This research displayed the new design of a 90 nm CMOS technology transimpedance amplifier (TIA) with current mirror executed. The goal and challenge in this research are to arrive at low consumption of power while activating other required performances. Integrated circuits CMOS(Complimentary Metal-Oxide Semiconductor) tend to be the best technology achieving the desired level of integration with appropriate speed, cost, and gain for this were used. The proposed transimpedance amplifier (TIA) consists of a common-gate (CG) topology with a current mirror to increase TIA gain and common-source (CS) TIA with the active feedback resistor. In addition, to verify the proposed TIA performance, circuit simulations are done in NI Multisim 14.1 using 90nm CMOS technology parameters. Therefore, the simulation results of the proposed TIA for 90 nm CMOS technology indicate a transimpedance gain of 66.63 dBΩ with -3dB frequency bandwidth of around 1.0 GHz for input capacitance of 250 fF, input-referred noise of 25.413 pA/ and with the power consumption of only 1.08m at 1V supply voltage. This low power consumption and supply voltage are the main emphases of this work in comparison with other research literature.


INTRODUCTION
Transimpedance amplifier (TIA) circuits in optical fiber networks play an important role in the optical fiber networks (Ota and Swartz, 1990). Besides long-haul fiber optic networks, optical communications are rapidly expanding into shorter distance, lower cost applications (Phang and Johns, 2001). The TIA must meet rigid specifications such as low input impedance to relatively high photodiode efficiency and thus achieve wide bandwidth, low noise to optimize receiver sensitivity, low cost area and low power consumption (Hassan and Zimmermann, 2012).
Besides, the scaling of the CMOS (Complementary Metal-Oxide Semiconductor) procedure to the range of nanometers enables the design of low-cost and high speedanalog CMOS circuit. However, the stacking of circuits is limited by the supply voltage scaling in nanometer CMOS technologies. It, therefore, limits gain and speed overall (Muller and Leblebici,2007). CMOS technology process combines devices formed by n-channel and p-channel in such a way to reduce the standby current by orders of magnitude relative to pure NMOS and PMOS implementations. No direct current can pass from V DD to ground as a CMOS appreciable current can rise during switching transients, and hence, a current exists only during small fraction of time during device operation (Pimbley et al.,1989).

Current Mirror
This paper presents an optical receiver based on an NMOS current mirror. This current mirror input was used to execute feedback current amplifiers which are capable of sensing the input current with low input resistance and amplifying it at a high impedance node, at the output (Hassan and Zimmermann., 2012). In Fig. (1), we note that the drain-gate voltage of the ambient is zero; therefore, the channel does not exist at the drain, and we see that the two transistors and operates in the saturation region if the threshold is positive. The current that flows in the drain of is mirrored to the drain of (Gray, 2001).

Common-Gate Amplifier
The common-gate (CG) amplifier is shown in Fig. (2a), the common-gate senses the input at the source and generates the output at the drain. The gate is connected to the DC voltage to establish proper operating conditions.

Fig. 2:(a) (CG)with direct coupling at input.(b) (CG)stage with capacitive coupling at input
We see that bias current flows through the source of the input signal. In illustrated figure (2b), can be biased by a constant current source, with the signal being capacitively connected to the circuit (Razavi, 2001). If the input increases by a small value, , the gate-source voltage of decreases by the same number, thus decreasing the drain current by and increasing V by .Then the voltage gain is positive and equal to: (1) If or is high enough, we can get a high gain, but the drain voltage, , still has to be above to make sure is saturated (Razavi, 2014).

The Design of Proposed (TIA) Circuit
In this section, we will present the design of the transimpedance amplifier (TIA) structure with current mirror implemented in a low-voltage (1V) and 90 nm CMOS technology as shown in Fig. (3). The proposed TIA topology involves a common-gate (CG) TIA and common-source (CS) TIA, with active feedback resistor and the current mirror to increase the gain in transimpedance. This work is a development of previous research (Phang, 2001). In this work, NI Multisim 14.1 Software was used to simulate the proposed transimpedance amplifier. It is based upon PSpice circuit solver engine which enable circuits to be solved on mathematical conversion point.

Fig. 3: Proposed low-voltage optical preamplifier
When the light is incident on the photodiode, it will convert the light into a suitable current. The input capacitance (250 fF) built in was attached parallel to the photodiode. The input capacitance is inversely proportional to the bandwidth frequency as the input capacitance increases, the bandwidth frequency decreases and this is due to the photodiode limitations that affect input capacitance.
Additionally, the circuit output is connected to another capacitance (250 fF output load capacitance) built in. The current from the photodiode would then move through the NMOS transistor representing the common-gate (CG) amplifier operating in the saturation region.
Therefore, the signal exiting in the drain terminal for passes through the node which in turn passes the signal through the gates of each of the and NMOS transistors representing the common source (CS) amplifier. As a result, the current in the transistor will be similar to the current in the transistor, then this current is called "current mirror" as previously stated and used to bias the NMOS transistor. After the signal is released from the transistor drain terminal, the current passes through the NMOS transistor (act as a resistor), representing a common-gate amplifier. Then transistor becomes a part of the feedback stage (negative feedback) by which the voltage at the output is converted into a current back to input, which is unprecedented here and for the first time, in addition, an active feedback loop connected to the input node was used, which ensures that there is no real resistance but built in NMOS channel resistance. Then, the amplification stage of the signal will be completed. Fig. (3) also shows that there are two PMOS transistors and which function as "current sources" as used to maintain the current stability in the circuit. Now, after reviewing the circuit operation we will look at the internal variables for each type of NMOS and PMOS transistor as shown in (Table 1). After entering and simulating these variables for the NMOS and PMOS transistors, we obtained the best results as shown in the low voltage (1V) supply (Table 2) concluding: high gain, wide bandwidth, low power consumption, and low noise at high frequencies.

Analysis of the Proposed Design
For circuit analysis, we will use the optical preamplifier small signal circuit as an illustration in Fig. (4). First of all, there are some simplifications were made: The main parasitic have been collected together into admittances , , and as follows: (2) (3) Where is the photodiode capacitance, is the capacitance of output load, while and are gate-to-source and drain-to-bulk parasitic capacitances respectively within the circuit.

Fig. 4: Small-signal circuit of the transimpedance amplifier
Now, we can draw the TIA Signal Flow Graph (SFG) as shown in Fig. (5) for proposed schematic circuit design. This figure shows how the SFG circuit structure reflects that of the circuit. We may redraw the SFG as shown in Fig. (6) to explain the loops in a feedback form. We note that the TIA consists of the following feedback loops: , is the loop (transconductance feedback) for the common gate topology of transistor , while, , is a loop (feedback) that passes from the input node to the gate of conducting to . As for loop, , it is around transistor through resistor .
Where is the forward Transimpedance path from to , While and is equal: (8) By combining for the admittances equations , , , and , it is possible to obtain the following formula for the ( gain) transimpedance gain: And the coefficients of the denominator are given by: Where is the transconductance between the drain to source for transistor and equals: Note that at (DC gain), the transimpedance gain becomes:

Bandwidth Modeling
As we know, bandwidth and sensitivity are the critical performance characteristics of any optical preamplifier. The bandwidth is worked out through the circuit frequency response. We'll improvise a simple model of the input impedance of the proposed TIA in the process. We can estimate the proposed TIA bandwidth. To find this approximation, the simplification of the SFG circuit and the identification of the dominant terms in each branch are included. From Fig. (7), we note that the first initiation of simplification, and the feedback loop locally around and were eventually reduced. We notice according to equation (9) that the transimpedance gain is proportional to ( ), and so is not too smaller than , therefore we cannot neglect ; but only at high frequencies is typically very small and can be neglected at this stage, so we can make the approximation that: From to , branches are combined at: Fig. 7: Simplified SFG for the signal path As such, we can minimize the entire SFG, as shown in Fig. (7), which can be schematically depicted in Fig. (8) when collapsed. We infer an important result from the input representation because it tells us that Resistor-Capacitor network can model the input of the TIA preamplifier, and that the pole (dominant) is simply the reversal of RC time constant given by: (12) To find the bandwidth from equation (12), we must extract , which represents the TIA's input resistance and is typically low, and then we must find equivalent for this proposed design of the circuit. Where:

Model of feedback path
By substituting equation (13) and (14) into equation (12) obtain: We know that, bandwidth, gain and noise are important requirements for circuit design, with design pre-requisites such as supply voltage and input capacitance influencing each.
The simulated TIA came at low supply voltage (1V) with short channel 90 nm CMOS ( : 0.1V NMOS and -0.8V PMOS) and alongside other parameters as noted as in (Table 1). So, as shown in Fig. (10), we obtained the best results, where the transimpedance gain was 66.63 dBΩ while -3dB bandwidth was around 1.0 GHz.

Noise Analysis
The noise characteristics of the transimpedance amplifier regarding the noise current spectral density referred to input or the corresponding reference noise current spectral density are of extreme importance for evaluating the sensitivity of the entire front-end optical receiver (Sackinger, 2005), (Vanisri and Toumazou,1995). As we know, a TIA sensitivity is constraint by its efficiency noise performance. At high TIA bandwidth, the dominant noise is the thermal noise. Fig. (11) illustrates the thermal noise sources found within the TIA with low voltage. This process can be achieved by transforming each noise term in the SFG back to the input node (Ochoa,1999). This analysis was shown in Fig. (12).
Equation (17), showed that the noise fraction of can be ignored at low frequencies where: An injected noise current into node is equivalent to a current as if it is injected at the circuit input. This will lead to the fact that at DC, the net noise fraction of is zero, and effectively negligible. As a result, cascade configuration devices such as do not give out large noise at low frequencies (Buchwald,1995). Regarding , we see that this noise represents also input-referred, so The noise current fraction I n5b , (similar to the noise component of ) is injected into node , making its contribution (i.e input-referred) as We note that from equation (19) for much of the passband, As a consequence, noise currents entering into node are effectively input-referred. This means that node is from a noise perspective virtually identical to the input node.
Finally, to calculate the TIA optical preamplifier's total input-referred noise current density, by integrating the effects of all of the individual noise components we get: Where the constituent parameters are:

Whereas
is Bolt mann's constant (1.38 and is the absolute temperature in Kelvin and is the excess noise factor and is the transconductance of the device. By using NI Multisim 14.1 simulation and achieving the best results at the maximum gain level, the input-referred noise current density is reduced and its flatness across the passband is equal to as shown in Fig. (13).

Fig. 13: Simulated input-referred noise of proposed TIA
Finally, (Table 3) illustrates the performance of the proposed (TIA). The main goal of this research is to operate the low-voltage circuit and reduce the power consumption of the proposed (TIA) circuit, and as is evident from (Table 3), the proposed (TIA) circuit topology consumes significantly less than other designs published. It is the principal goal of the proposed research.

CONCLUSION
In this paper, a new design topology is reported for the transimpedance amplifier (TIA) for use in an optical communication. A TIA with low voltage and high gain and low power consumption and low noise is designed based on the novel topology and then, the proposed design is simulated with 1V 90nm CMOS technology and with current mirror and active feedback employing CG amplifier to extend the transimpedance gain and bandwidth. The simulation results show the transimpedance gain of 66.63 dBΩ with a bandwidth of around 1.0 G and photodiode parasitic capacitance of 250fF. Average input-referred noise current spectral density is equal to 25.413PA/ .